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Tower Semiconductor: the constraint moved downstream of the fab
The bottleneck has migrated from lithography to packaging and power. That changes who captures the margin on every incremental unit.
Evidence · 4 cards
The mechanism is straightforward. Advanced packaging capacity is allocated a year ahead, so a unit that clears wafer test still waits on a substrate slot before it can be recognised as revenue. That queue, not the fab, is what sets the quarterly number.
Three data points support it. Packaging capacity bookings at the two qualified subcontractors are sold out through the next four quarters, disclosed lead times extended again last month, and the company's own deferred revenue balance rose faster than billings for the second consecutive period.
The position: long on Tower Semiconductor, entry locked at publication and the exit dated rather than open-ended. The target is stated in the call block above and the horizon with it. Sized to the catalyst rather than to conviction, with the invalidation written into the kill-switch card instead of left implicit.
The risk is a demand shock large enough to make the supply argument irrelevant. If end demand rolls over, a packaging queue stops being a constraint and starts being idle capacity, and the mix argument goes with it.
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